1. Field of the Invention
The invention is directed to a digital voltage translator which accepts an input voltage which transitions within a lower voltage range and accurately provides an output voltage signal which transitions within a higher voltage range. More specifically, the present invention is directed to a digital voltage translator which operates with a wide range of input voltages and to its method of operation.
2. Discussion of the Related Art
Voltage translating circuits are known for interfacing between circuits which use digital signals which transition within different voltage ranges. In the memory 20 integrated circuit area, such as in BSRAM memories, such circuits are used to translate a signal from logic circuits, which typically produce digital signals which transition within a voltage range of, e.g., 0 to 2.5 v to memory circuits which typically produce digital signals which transition within a voltage range of 0 to 3.5 v.
One such voltage translator is described in the specification entitled "250 Megahertz Voltage Scaleable CMOS Input Buffer", issued by the Intel Platform Architecture Laboratory on Mar. 12, 1996. This paper describes a one inverter shift latch and a two inverter shift latch for providing the voltage translation functions. The single inverter shift latch is shown in FIG. 1. The circuits described in the paper are designed to provide a voltage translation which will work with digital input signals which transition with a range of 0 to 1.8 v to 2.5 v and provide output signals which transition in the range of 0 to 3.1 to 3.5 volts. Although the circuitry described in this article functions well with the input voltages which it was designed for, there is increasing demand in the industry to use even lower voltages for certain logic functions. However, as the input voltage transition range in the FIG. 1 circuit is decreased, the circuitry no longer accurately produces optimum output signals. In order to accurately translate the input signals, a translator circuit must produce output signals which have a high to low (falling edge) signal level transition which takes the same amount of time as a low to high (rising edge) signal level transition. In order for this to occur, the FIG. 1 circuit transistor 107 (FIG. 1) provides less drive than does transistor 103. This compensates for the extra transistor 105 which is in the output signal path to equalize the time delay when the output signal transitions following an input signal transition. However, as the range in which the logic circuit voltage transitions decreases the voltage applied to the gates of the transistors 107 and 103 is similarly reduced which decreases the drive of these transistors. As a consequence, at some point the lowered input voltage has a negative effect on the performance of the circuit. This effect is mainly seen on transistor 107 since it provides less drive than transistor 103. As a result, the time for the high to low and low to high transitions of the output signal are no longer the same. This can be seen from a comparison of FIG. 2 which shows the high-to-low and low-to-high output signals Vout.sub.1, Vout.sub.2 of the FIG. 1 circuit when the input voltage transitions in the range of 0 to 2.5 volts and FIG. 3 which shows these same output signals when the input voltage transitions are in the range of 0 to 1.4 volts. FIG. 2 shows the crossing points for the output voltage at a voltage of approximately VDD.sub.2 /2 where VDD.sub.2 is the upper voltage for the output signal when there is a low to high and high to low transition at the input signal. The rising and falling edge output signal transitions occur at virtually the same time following the input signal transition. However, as shown in FIG. 3, when a decreased input voltage range is used, e.g. 0 to 1.4 v, the rising and falling edges of the output voltage no longer occur at the same time. They are skewed by the time period .DELTA.t. This could cause timing problems in downstream memory circuits.
In addition, the voltage translating circuits described in the above-referenced article and in FIG. 1 provide an output signal at all times, that is the output signal will always transition whenever there is a transition in the input signal. Thus, during power down modes, the FIG. 1 circuit can still undergo transitions which will affect downstream circuits and cause undesired current drain.